27 lines
595 B
Text
27 lines
595 B
Text
# We look for a Delay-block, its inport connected to an outport that has a signal
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delay:RAM_Delay
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delay_in:RAM_InPort
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delay_has_input:RAM_hasInPort (delay -> delay_in)
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some_outport:RAM_OutPort
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delay_in_conn:RAM_link (some_outport -> delay_in)
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in_signal:RAM_Signal
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port_has_signal:RAM_hasSignal (some_outport -> in_signal)
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# State of Delay block... (will be updated in RHS)
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state:RAM_State {
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# Attention: you MUST match the existing attribute, in order to force an UDPATE of the attribute, rather than CREATION
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RAM_x = `True`;
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}
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delay_to_state:RAM_delay2State (delay -> state)
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