# We look for a Delay-block, its inport connected to an outport that has a signal

delay:RAM_Delay

delay_in:RAM_InPort

delay_has_input:RAM_hasInPort (delay -> delay_in)

some_outport:RAM_OutPort

delay_in_conn:RAM_link (some_outport -> delay_in)

in_signal:RAM_Signal

port_has_signal:RAM_hasSignal (some_outport -> in_signal)



# State of Delay block... (will be updated in RHS)

state:RAM_State {
  # Attention: you MUST match the existing attribute, in order to force an UDPATE of the attribute, rather than CREATION
  
  RAM_x = `True`;
}

delay_to_state:RAM_delay2State (delay -> state)