129 lines
2.9 KiB
Text
129 lines
2.9 KiB
Text
Block:Class {
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abstract = True;
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}
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InPort:Class {
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# abstract = True;
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}
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OutPort:Class {
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# abstract = True;
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}
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hasInPort:Association (Block -> InPort) {
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# Every Port contained by exactly one Block:
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source_lower_cardinality = 1;
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source_upper_cardinality = 1;
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}
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hasOutPort:Association (Block -> OutPort) {
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# Every Port contained by exactly one Block:
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source_lower_cardinality = 1;
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source_upper_cardinality = 1;
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}
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link:Association (OutPort -> InPort) {
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#abstract = True;
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# Every InPort connected to exactly one OutPort
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source_lower_cardinality = 1;
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source_upper_cardinality = 1;
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}
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# In- and Out-Ports are labeled:
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# hasInPort_label:AttributeLink (hasInPort -> String) {
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# name = "label";
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# optional = False;
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# }
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# hasOutPort_label:AttributeLink (hasOutPort -> String) {
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# name = "label";
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# optional = False;
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# }
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# Function Block: pure function that computes outputs based on inputs
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Function:Class
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:Inheritance (Function -> Block)
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Function_func:AttributeLink (Function -> ActionCode) {
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name = "func";
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optional = False;
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}
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DetailedFunction:Class
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:Inheritance (DetailedFunction -> Function)
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VeryDetailedFunction:Class
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:Inheritance (VeryDetailedFunction -> DetailedFunction)
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# Delay Block
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Delay:Class {
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constraint = ```
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errors = []
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num_inports = len(get_outgoing(this, "hasInPort"))
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num_outports = len(get_outgoing(this, "hasOutPort"))
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if num_inports != 1:
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errors.append(f"Delay block must have one inport, instead got {num_inports}")
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in_type = None
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else:
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in_type = get_type_name(get_target(get_outgoing(this, "hasInPort")[0]))
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if num_outports != 1:
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errors.append(f"Delay block must have one inport, instead got {num_outports}")
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out_type = None
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else:
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out_type = get_type_name(get_target(get_outgoing(this, "hasOutPort")[0]))
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# if in_type != None and out_type != None and in_type[0:3] != out_type[0:3]:
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# errors.append(f"Inport type ({in_type}) differs from outport type ({out_type})")
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errors
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```;
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}
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:Inheritance (Delay -> Block)
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# Object Diagrams are statically typed, so we must create in/out-ports, and MemorySlots for all primitive types:
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# # Port types
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# BoolInPort:Class
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# IntInPort:Class
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# StrInPort:Class
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# BoolOutPort:Class
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# IntOutPort:Class
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# StrOutPort:Class
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# :Inheritance (BoolInPort -> InPort)
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# :Inheritance (IntInPort -> InPort)
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# :Inheritance (StrInPort -> InPort)
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# :Inheritance (BoolOutPort -> OutPort)
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# :Inheritance (IntOutPort -> OutPort)
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# :Inheritance (StrOutPort -> OutPort)
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# # Link types
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# boolLink:Association (BoolOutPort -> BoolInPort)
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# intLink:Association (IntOutPort -> IntInPort)
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# strLink:Association (StrOutPort -> StrInPort)
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# :Inheritance (boolLink -> link)
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# :Inheritance (intLink -> link)
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# :Inheritance (strLink -> link)
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# # Delay block types
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# BoolDelay:Class
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# IntDelay:Class
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# StrDelay:Class
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# :Inheritance (BoolDelay -> Delay)
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# :Inheritance (IntDelay -> Delay)
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# :Inheritance (StrDelay -> Delay)
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