40 lines
1 KiB
Text
40 lines
1 KiB
Text
# We look for a Delay-block, its inport connected to an outport that has a signal
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delay:RAM_Delay
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delay_inport:RAM_InPort
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delay_has_inport:RAM_hasInPort (delay -> delay_inport)
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some_outport:RAM_OutPort
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delay_in_conn:RAM_link (some_outport -> delay_inport)
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in_signal:RAM_Signal {
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# If the signal is already equal to the state, don't match:
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# (without this, the rule could keep firing)
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RAM_x = `get_value(this) != get_slot_value(matched('state'), 'x')`;
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}
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port_in_signal:RAM_hasSignal (some_outport -> in_signal)
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# State of Delay block... (will be updated in RHS)
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state:RAM_State {
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# Attention: you MUST match the existing attribute, in order to force an UDPATE of the attribute, rather than CREATION
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RAM_x = `True`;
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}
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delay_to_state:RAM_delay2State (delay -> state)
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# Only update Delay block state IF after its output signal has been computed:
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delay_outport:RAM_OutPort
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delay_has_outport:RAM_hasOutPort (delay -> delay_outport)
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out_signal:RAM_Signal
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delay_out_signal:RAM_hasSignal (delay_outport -> out_signal)
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