18 lines
335 B
Text
18 lines
335 B
Text
# Our entire LHS (don't delete anything):
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delay:RAM_Delay
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delay_out:RAM_OutPort
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delay_has_output:RAM_hasOutPort (delay -> delay_out)
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state:RAM_State
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delay_to_state:RAM_delay2State (delay -> state)
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# To create:
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new_signal:RAM_Signal {
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RAM_x = `get_slot_value(matched('state'), 'x')`;
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}
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:RAM_hasSignal (delay_out -> new_signal)
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