Rewrite the 'rewriter' + Added transformation schedule to CBD example, simplifying the rules

examples/cbd/models/r_advance_time_nac.od

@@ -1,28 +1,6 @@
+# We cannot advance time until all outports have signals
 
-# If there is a Delay-block whose input signal differs from its state, we cannot yet advance time:
-
-delay:RAM_Delay
-
-delay_in:RAM_InPort
-
-delay_has_input:RAM_hasInPort (delay -> delay_in)
-
-some_outport:RAM_OutPort
-
-delay_in_conn:RAM_link (some_outport -> delay_in)
-
-in_signal:RAM_Signal
-
-port_has_signal:RAM_hasSignal (some_outport -> in_signal)
-
-state:RAM_State {
-  RAM_x = `get_slot_value(matched('in_signal'), 'x') != get_value(this)`;
-}
-
-delay_to_state:RAM_delay2State (delay -> state)
-
-
-# Also, we cannot advance time until all outports have signals:
+# BTW, this NAC is not really necessary, because our schedule already will only try to match 'advance_time' when no other actions are enabled
 
 :GlobalCondition {
   condition = ```

examples/cbd/models/r_advance_time_rhs.od

@@ -2,6 +2,8 @@ clock:RAM_Clock {
   RAM_time = `get_value(this) + 1`;
 }
 
+# Delete all Signals:
+
 :GlobalCondition {
   condition = ```
     for _, signal in get_all_instances("Signal"):

examples/cbd/models/r_delay_in_lhs.od

@@ -2,17 +2,22 @@
 
 delay:RAM_Delay
 
-delay_in:RAM_InPort
+delay_inport:RAM_InPort
 
-delay_has_input:RAM_hasInPort (delay -> delay_in)
+delay_has_inport:RAM_hasInPort (delay -> delay_inport)
 
 some_outport:RAM_OutPort
 
-delay_in_conn:RAM_link (some_outport -> delay_in)
+delay_in_conn:RAM_link (some_outport -> delay_inport)
 
-in_signal:RAM_Signal
+in_signal:RAM_Signal {
+  # If the signal is already equal to the state, don't match:
+  # (without this, the rule could keep firing)
 
-port_has_signal:RAM_hasSignal (some_outport -> in_signal)
+  RAM_x = `get_value(this) != get_slot_value(matched('state'), 'x')`;
+}
+
+port_in_signal:RAM_hasSignal (some_outport -> in_signal)
 
 
 
@@ -20,8 +25,16 @@ port_has_signal:RAM_hasSignal (some_outport -> in_signal)
 
 state:RAM_State {
   # Attention: you MUST match the existing attribute, in order to force an UDPATE of the attribute, rather than CREATION
-  
   RAM_x = `True`;
 }
 
 delay_to_state:RAM_delay2State (delay -> state)
+
+
+
+# Only update Delay block state IF after its output signal has been computed:
+
+delay_outport:RAM_OutPort
+delay_has_outport:RAM_hasOutPort (delay -> delay_outport)
+out_signal:RAM_Signal
+delay_out_signal:RAM_hasSignal (delay_outport -> out_signal)

examples/cbd/models/r_delay_in_nac.od

@@ -1,6 +1,5 @@
-state:RAM_State # <- must repeat elements from LHS that we refer to
 
-in_signal:RAM_Signal {
-  # If the signal is already equal to the state, the NAC holds:
-  RAM_x = `get_value(this) == get_slot_value(matched('state'), 'x')`;
-}
+:GlobalCondition {
+  # No NAC
+  condition = `False`;
+}

examples/cbd/models/r_delay_in_rhs.od

@@ -2,17 +2,20 @@
 
 delay:RAM_Delay
 
-delay_in:RAM_InPort
+delay_inport:RAM_InPort
 
-delay_has_input:RAM_hasOutPort (delay -> delay_in)
+delay_has_inport:RAM_hasOutPort (delay -> delay_inport)
 
 some_outport:RAM_OutPort
 
-delay_in_conn:RAM_link (some_outport -> delay_in)
+delay_in_conn:RAM_link (some_outport -> delay_inport)
 
-in_signal:RAM_Signal
+in_signal:RAM_Signal {
+  # Need to repeat this slot, otherwise it will be deleted:
+  RAM_x = `get_value(this)`;
+}
 
-port_has_signal:RAM_hasSignal (some_outport -> in_signal)
+port_in_signal:RAM_hasSignal (some_outport -> in_signal)
 
 state:RAM_State {
   # Update:
@@ -24,3 +27,9 @@ state:RAM_State {
 }
 
 delay_to_state:RAM_delay2State (delay -> state)
+
+
+delay_outport:RAM_OutPort
+delay_has_outport:RAM_hasOutPort (delay -> delay_outport)
+out_signal:RAM_Signal
+delay_out_signal:RAM_hasSignal (delay_outport -> out_signal)

examples/cbd/models/r_delay_out_lhs.od

@@ -10,5 +10,3 @@ delay_has_output:RAM_hasOutPort (delay -> delay_out)
 state:RAM_State
 
 delay_to_state:RAM_delay2State (delay -> state)
-
-clock:RAM_Clock

examples/cbd/models/r_delay_out_rhs.od

@@ -10,8 +10,6 @@ state:RAM_State
 
 delay_to_state:RAM_delay2State (delay -> state)
 
-clock:RAM_Clock
-
 # To create:
 
 new_signal:RAM_Signal {

examples/cbd/models/r_function_out_lhs.od

@@ -18,5 +18,3 @@ f:RAM_Function {
 f_outport:RAM_OutPort
 
 f_has_outport:RAM_hasOutPort (f -> f_outport)
-
-clock:RAM_Clock

examples/cbd/models/r_function_out_rhs.od

@@ -6,8 +6,6 @@ f_outport:RAM_OutPort
 
 f_has_outport:RAM_hasOutPort (f -> f_outport)
 
-clock:RAM_Clock
-
 # To create:
 
 f_out_signal:RAM_Signal {