Rewrite the 'rewriter' + Added transformation schedule to CBD example, simplifying the rules

examples/cbd/models/r_advance_time_nac.od

@@ -1,28 +1,6 @@
+# We cannot advance time until all outports have signals
 
-# If there is a Delay-block whose input signal differs from its state, we cannot yet advance time:
-
-delay:RAM_Delay
-
-delay_in:RAM_InPort
-
-delay_has_input:RAM_hasInPort (delay -> delay_in)
-
-some_outport:RAM_OutPort
-
-delay_in_conn:RAM_link (some_outport -> delay_in)
-
-in_signal:RAM_Signal
-
-port_has_signal:RAM_hasSignal (some_outport -> in_signal)
-
-state:RAM_State {
-  RAM_x = `get_slot_value(matched('in_signal'), 'x') != get_value(this)`;
-}
-
-delay_to_state:RAM_delay2State (delay -> state)
-
-
-# Also, we cannot advance time until all outports have signals:
+# BTW, this NAC is not really necessary, because our schedule already will only try to match 'advance_time' when no other actions are enabled
 
 :GlobalCondition {
   condition = ```

examples/cbd/models/r_advance_time_rhs.od

@@ -2,6 +2,8 @@ clock:RAM_Clock {
   RAM_time = `get_value(this) + 1`;
 }
 
+# Delete all Signals:
+
 :GlobalCondition {
   condition = ```
     for _, signal in get_all_instances("Signal"):

examples/cbd/models/r_delay_in_lhs.od

@@ -2,17 +2,22 @@
 
 delay:RAM_Delay
 
-delay_in:RAM_InPort
+delay_inport:RAM_InPort
 
-delay_has_input:RAM_hasInPort (delay -> delay_in)
+delay_has_inport:RAM_hasInPort (delay -> delay_inport)
 
 some_outport:RAM_OutPort
 
-delay_in_conn:RAM_link (some_outport -> delay_in)
+delay_in_conn:RAM_link (some_outport -> delay_inport)
 
-in_signal:RAM_Signal
+in_signal:RAM_Signal {
+  # If the signal is already equal to the state, don't match:
+  # (without this, the rule could keep firing)
 
-port_has_signal:RAM_hasSignal (some_outport -> in_signal)
+  RAM_x = `get_value(this) != get_slot_value(matched('state'), 'x')`;
+}
+
+port_in_signal:RAM_hasSignal (some_outport -> in_signal)
 
 
 
@@ -20,8 +25,16 @@ port_has_signal:RAM_hasSignal (some_outport -> in_signal)
 
 state:RAM_State {
   # Attention: you MUST match the existing attribute, in order to force an UDPATE of the attribute, rather than CREATION
-  
   RAM_x = `True`;
 }
 
 delay_to_state:RAM_delay2State (delay -> state)
+
+
+
+# Only update Delay block state IF after its output signal has been computed:
+
+delay_outport:RAM_OutPort
+delay_has_outport:RAM_hasOutPort (delay -> delay_outport)
+out_signal:RAM_Signal
+delay_out_signal:RAM_hasSignal (delay_outport -> out_signal)

examples/cbd/models/r_delay_in_nac.od

@@ -1,6 +1,5 @@
-state:RAM_State # <- must repeat elements from LHS that we refer to
 
-in_signal:RAM_Signal {
-  # If the signal is already equal to the state, the NAC holds:
-  RAM_x = `get_value(this) == get_slot_value(matched('state'), 'x')`;
-}
+:GlobalCondition {
+  # No NAC
+  condition = `False`;
+}

examples/cbd/models/r_delay_in_rhs.od

@@ -2,17 +2,20 @@
 
 delay:RAM_Delay
 
-delay_in:RAM_InPort
+delay_inport:RAM_InPort
 
-delay_has_input:RAM_hasOutPort (delay -> delay_in)
+delay_has_inport:RAM_hasOutPort (delay -> delay_inport)
 
 some_outport:RAM_OutPort
 
-delay_in_conn:RAM_link (some_outport -> delay_in)
+delay_in_conn:RAM_link (some_outport -> delay_inport)
 
-in_signal:RAM_Signal
+in_signal:RAM_Signal {
+  # Need to repeat this slot, otherwise it will be deleted:
+  RAM_x = `get_value(this)`;
+}
 
-port_has_signal:RAM_hasSignal (some_outport -> in_signal)
+port_in_signal:RAM_hasSignal (some_outport -> in_signal)
 
 state:RAM_State {
   # Update:
@@ -24,3 +27,9 @@ state:RAM_State {
 }
 
 delay_to_state:RAM_delay2State (delay -> state)
+
+
+delay_outport:RAM_OutPort
+delay_has_outport:RAM_hasOutPort (delay -> delay_outport)
+out_signal:RAM_Signal
+delay_out_signal:RAM_hasSignal (delay_outport -> out_signal)

examples/cbd/models/r_delay_out_lhs.od

@@ -10,5 +10,3 @@ delay_has_output:RAM_hasOutPort (delay -> delay_out)
 state:RAM_State
 
 delay_to_state:RAM_delay2State (delay -> state)
-
-clock:RAM_Clock

examples/cbd/models/r_delay_out_rhs.od

@@ -10,8 +10,6 @@ state:RAM_State
 
 delay_to_state:RAM_delay2State (delay -> state)
 
-clock:RAM_Clock
-
 # To create:
 
 new_signal:RAM_Signal {

examples/cbd/models/r_function_out_lhs.od

@@ -18,5 +18,3 @@ f:RAM_Function {
 f_outport:RAM_OutPort
 
 f_has_outport:RAM_hasOutPort (f -> f_outport)
-
-clock:RAM_Clock

examples/cbd/models/r_function_out_rhs.od

@@ -6,8 +6,6 @@ f_outport:RAM_OutPort
 
 f_has_outport:RAM_hasOutPort (f -> f_outport)
 
-clock:RAM_Clock
-
 # To create:
 
 f_out_signal:RAM_Signal {

examples/cbd/runner.py

@@ -1,7 +1,10 @@
+import functools
+import pprint
+
 from state.devstate import DevState
 from bootstrap.scd import bootstrap_scd
 
-from framework.conformance import Conformance, render_conformance_check_result
+from api.od import ODAPI
 
 from concrete_syntax.common import indent
 from concrete_syntax.textual_od import renderer as od_renderer
@@ -14,8 +17,88 @@ from transformation.matcher.mvs_adapter import match_od
 from transformation.rewriter import rewrite
 from transformation.cloner import clone_od
 
+from examples.semantics.operational import simulator
+
 import models
 
+
+def match_rule(rule_name, od: ODAPI, lhs, nac):
+    lhs_matcher = match_od(state,
+        host_m=od.m,
+        host_mm=od.mm,
+        pattern_m=lhs,
+        pattern_mm=mm_rt_ram)
+
+    try:
+        for i, lhs_match in enumerate(lhs_matcher):
+            nac_matcher = match_od(state,
+                host_m=od.m,
+                host_mm=od.mm,
+                pattern_m=nac,
+                pattern_mm=mm_rt_ram,
+                pivot=lhs_match)
+
+            try:
+                for j, nac_match in enumerate(nac_matcher):
+                    break # there may be more NAC-matches, but we already now enough -> proceed to next lhs_match
+                else:
+                    yield lhs_match # got match
+            except Exception as e:
+                # Make exceptions raised in eval'ed code easier to trace:
+                e.add_note(f"while matching NAC of '{rule_name}'")
+                raise
+
+    except Exception as e:
+        # Make exceptions raised in eval'ed code easier to trace:
+        e.add_note(f"while matching LHS of '{rule_name}'")
+        raise
+
+def exec_action(rule_name, od: ODAPI, lhs, rhs, lhs_match):
+    # copy these, will be overwritten in-place
+    cloned_m = clone_od(state, od.m, od.mm)
+    rhs_match = dict(lhs_match)
+
+    try:
+        rewrite(state,
+            lhs_m=lhs,
+            rhs_m=rhs,
+            pattern_mm=mm_rt_ram,
+            lhs_name_mapping=rhs_match,
+            host_m=cloned_m,
+            host_mm=od.mm)
+    except Exception as e:
+        # Make exceptions raised in eval'ed code easier to trace:
+        e.add_note(f"while executing RHS of '{rule_name}'")
+        raise
+
+    print("Updated match:\n" + indent(pp.pformat(rhs_match), 6))
+
+    return (ODAPI(state, cloned_m, od.mm), [f"executed rule '{rule_name}'"])
+
+pp = pprint.PrettyPrinter(depth=4)
+
+def attempt_rules(od: ODAPI, rule_dict):
+    at_least_one_match = False
+    for rule_name, rule in rule_dict.items():
+        for lhs_match in match_rule(rule_name, od, rule["lhs"], rule["nac"]):
+            # We got a match!
+            yield (rule_name + '\n' + indent(pp.pformat(lhs_match), 6),
+                functools.partial(exec_action,
+                    rule_name, od, rule["lhs"], rule["rhs"], lhs_match))
+            at_least_one_match = True
+    return at_least_one_match
+
+def get_actions(od: ODAPI):
+    # transformation schedule
+    rule_advance_time = rules["advance_time"]
+    rules_not_advancing_time = { rule_name: rule for rule_name, rule in rules.items() if rule_name != "advance_time" }
+    
+    at_least_one_match = yield from attempt_rules(od, rules_not_advancing_time)
+    if not at_least_one_match:
+        yield from attempt_rules(od, {"advance_time": rule_advance_time})
+
+
+
 state = DevState()
 scd_mmm = bootstrap_scd(state)
 
@@ -26,86 +109,17 @@ mm_rt_ram, rules = models.get_rules(state, mm_rt)
 # print("RT-MM")
 # print(make_plantuml_url(plantuml.render_class_diagram(state, mm_rt)))
 
-
 # print("RAMIFIED RT-MM")
 # print(make_plantuml_url(plantuml.render_class_diagram(state, mm_rt_ram)))
 
-m_rt = m_rt_initial
+sim = simulator.Simulator(
+    action_generator=get_actions,
+    # decision_maker=simulator.InteractiveDecisionMaker(auto_proceed=False),
+    decision_maker=simulator.RandomDecisionMaker(seed=0),
+    termination_condition=lambda od: "Time is up" if od.get_slot_value(od.get_all_instances("Clock")[0][1], "time") >= 10 else None,
+    check_conformance=True,
+    verbose=True,
+    renderer=lambda od: od_renderer.render_od(state, od.m, od.mm, hide_names=False),
+)
 
-def get_matches():
-    for rule_name, rule in rules.items():
-        lhs = rule["lhs"]
-
-        lhs_matcher = match_od(state,
-            host_m=m_rt,
-            host_mm=mm_rt,
-            pattern_m=lhs,
-            pattern_mm=mm_rt_ram)
-
-        try:
-            for i, lhs_match in enumerate(lhs_matcher):
-                nac_matcher = match_od(state,
-                    host_m=m_rt,
-                    host_mm=mm_rt,
-                    pattern_m=rule["nac"],
-                    pattern_mm=mm_rt_ram,
-                    pivot=lhs_match)
-
-                try:
-                    for j, nac_match in enumerate(nac_matcher):
-                        break # there may be more NAC-matches, but we already now enough
-                    else:
-                        # We got a match!
-                        yield (rule_name, lhs, rule["rhs"], lhs_match)
-                except Exception as e:
-                    # Make exceptions raised in eval'ed code easier to trace:
-                    e.add_note(f"while matching NAC of '{rule_name}'")
-                    raise
-
-        except Exception as e:
-            # Make exceptions raised in eval'ed code easier to trace:
-            e.add_note(f"while matching LHS of '{rule_name}'")
-            raise
-
-while True:
-    # print(make_graphviz_url(graphviz.render_object_diagram(state, m_rt, mm_rt)))
-    cs = od_renderer.render_od(state, m_rt, mm_rt, hide_names=False)
-    print(indent(cs, 6))
-    conf = Conformance(state, m_rt, mm_rt)
-    print(render_conformance_check_result(conf.check_nominal()))
-
-    matches = list(get_matches())
-
-    print(f"There are {len(matches)} matches.")
-    if len(matches) == 0:
-        break
-    rule_name, lhs, rhs, lhs_match = matches[0]
-
-
-                # txt = graphviz.render_package("Host", graphviz.render_object_diagram(state, m_rt, mm_rt))
-                # txt += graphviz.render_package("LHS", graphviz.render_object_diagram(state, lhs, mm_rt_ram))
-                # txt += graphviz.render_trace_match(state, lhs_match, lhs, m_rt, color="orange")
-                # match_urls.append(make_graphviz_url(txt))
-
-    print(f"executing rule '{rule_name}' ", lhs_match)
-
-    # copy or will be overwritten in-place
-    m_rt = clone_od(state, m_rt, mm_rt)
-    rhs_match = dict(lhs_match)
-    try:
-        rewrite(state,
-            lhs_m=lhs,
-            rhs_m=rhs,
-            pattern_mm=mm_rt_ram,
-            name_mapping=rhs_match,
-            host_m=m_rt,
-            host_mm=mm_rt)
-    except Exception as e:
-        # Make exceptions raised in eval'ed code easier to trace:
-        e.add_note(f"while executing RHS of '{rule_name}'")
-        raise
-
-    # import subprocess
-    # subprocess.run(["firefox", "--new-window", *match_urls])
-
-# get_actions(state, rules, m_rt_initial, mm_rt)
+sim.run(ODAPI(state, m_rt_initial, mm_rt))

examples/semantics/operational/simulator.py

@@ -36,7 +36,7 @@ class Simulator:
             print(*args)
 
     # Run simulation until termination condition satisfied
-    def run(self, od):
+    def run(self, od: ODAPI):
         self.__print("Start simulation")
         self.__print(f"Decision maker: {self.decision_maker}")
         step_counter = 0
@@ -112,8 +112,10 @@ class RandomDecisionMaker(DecisionMaker):
         return arr[i]
 
 class InteractiveDecisionMaker(DecisionMaker):
-    def __init__(self, msg="Select action:"):
+    # auto_proceed: whether to prompt if there is only one enabled action
+    def __init__(self, msg="Select action:", auto_proceed=False):
         self.msg = msg
+        self.auto_proceed = auto_proceed
 
     def __str__(self):
         return f"InteractiveDecisionMaker()"
@@ -125,6 +127,8 @@ class InteractiveDecisionMaker(DecisionMaker):
            arr.append(result)
         if len(arr) == 0:
            return
+        if len(arr) == 1 and self.auto_proceed:
+            return arr[0]
 
         def __choose():
            sys.stdout.write(f"{self.msg} ")