Refactor 'port' demo to include starting point for assignment

This commit is contained in:
Joeri Exelmans 2024-10-30 01:02:11 +01:00
parent 72c78c664f
commit 86610139d2
7 changed files with 300 additions and 16 deletions

View file

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import urllib.parse
from state.devstate import DevState
from bootstrap.scd import bootstrap_scd
from framework.conformance import Conformance, render_conformance_check_result
from concrete_syntax.textual_od import parser
from concrete_syntax.plantuml.renderer import render_object_diagram, render_class_diagram
from api.od import ODAPI
from examples.semantics.operational.simulator import Simulator, RandomDecisionMaker, InteractiveDecisionMaker
from examples.semantics.operational.port import models
from examples.semantics.operational.port.helpers import design_to_state, state_to_design, get_time
from examples.semantics.operational.port.renderer import render_port_textual, render_port_graphviz
# from examples.semantics.operational.port.joeris_solution import termination_condition, get_actions
from examples.semantics.operational.port.assignment import termination_condition, get_actions
state = DevState()
scd_mmm = bootstrap_scd(state) # Load meta-meta-model
### Load (meta-)models ###
def parse_and_check(m_cs: str, mm, descr: str):
m = parser.parse_od(
state,
m_text=m_cs,
mm=mm)
conf = Conformance(state, m, mm)
print(descr, "...", render_conformance_check_result(conf.check_nominal()))
return m
port_mm = parse_and_check(models.port_mm_cs, scd_mmm, "MM")
port_m = parse_and_check(models.port_m_cs, port_mm, "M")
port_rt_mm = parse_and_check(models.port_rt_mm_cs, scd_mmm, "RT-MM")
port_rt_m = parse_and_check(models.port_rt_m_cs, port_rt_mm, "RT-M")
print()
# print(render_class_diagram(state, port_rt_mm))
### Simulate ###
sim = Simulator(
action_generator=get_actions,
# decision_maker=RandomDecisionMaker(seed=2),
decision_maker=InteractiveDecisionMaker(),
termination_condition=termination_condition,
check_conformance=True,
verbose=True,
renderer=render_port_textual,
# renderer=render_port_graphviz,
)
od = ODAPI(state, port_rt_m, port_rt_mm)
sim.run(od)