(WIP) add CBD language

examples/cbd/models/m_fibonacci.od

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+adder:Function {
+  func = ```
+    n2_out = in0 + in1
+  ```;
+}
+n0_in:IntInPort
+n1_in:IntInPort
+n2_out:IntOutPort
+:hasInPort (adder -> n0_in)
+:hasInPort (adder -> n1_in)
+:hasOutPort (adder -> n2_out)
+
+
+
+d0:Delay
+d0_in:IntInPort
+d0_out:IntOutPort
+:hasInPort (d0 -> d0_in)
+:hasOutPort (d0 -> d0_out)
+
+
+
+d1:Delay
+d1_in:IntInPort
+d1_out:IntOutPort
+:hasInPort (d1 -> d1_in)
+:hasOutPort (d1 -> d1_out)
+
+
+
+:intLink (n2_out -> d1_in)
+:intLink (d1_out -> n1_in)
+:intLink (d1_out -> d0_in)
+:intLink (d1_out -> n0_in)

examples/cbd/models/m_fibonacci_initial.od

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+d0s:IntState {
+  state = 0;
+}
+d1s:IntState {
+  state = 1;
+}
+:delay2State (d0 -> d0s)
+:delay2State (d1 -> d1s)

examples/cbd/models/mm_design.od

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+Block:Class {
+  abstract = True;
+}
+
+InPort:Class {
+  abstract = True;
+}
+OutPort:Class {
+  abstract = True;
+}
+
+hasInPort:Association (Block -> InPort) {
+  # Every Port contained by exactly one Block:
+  source_lower_cardinality = 1;
+  source_upper_cardinality = 1;
+}
+hasOutPort:Association (Block -> OutPort) {
+  # Every Port contained by exactly one Block:
+  source_lower_cardinality = 1;
+  source_upper_cardinality = 1;
+}
+
+link:Association (OutPort -> InPort) {
+  #abstract = True;
+
+  # Every InPort connected to exactly one OutPort
+  source_lower_cardinality = 1;
+  source_upper_cardinality = 1;
+}
+
+
+# In- and Out-Ports are labeled:
+
+# hasInPort_label:AttributeLink (hasInPort -> String) {
+#   name = "label";
+#   optional = False;
+# }
+# hasOutPort_label:AttributeLink (hasOutPort -> String) {
+#   name = "label";
+#   optional = False;
+# }
+
+
+
+# Function Block: pure function that computes outputs based on inputs
+
+Function:Class
+:Inheritance (Function -> Block)
+
+Function_func:AttributeLink (Function -> ActionCode) {
+  name = "func";
+  optional = False;
+}
+
+DetailedFunction:Class
+:Inheritance (DetailedFunction -> Function)
+
+VeryDetailedFunction:Class
+:Inheritance (VeryDetailedFunction -> DetailedFunction)
+
+
+
+# Delay Block
+
+Delay:Class {
+  constraint = ```
+    errors = []
+    num_inports = len(get_outgoing(this, "hasInPort"))
+    num_outports = len(get_outgoing(this, "hasOutPort"))
+    if num_inports != 1:
+      errors.append(f"Delay block must have one inport, instead got {num_inports}")
+      in_type = None
+    else:
+      in_type = get_type_name(get_target(get_outgoing(this, "hasInPort")[0]))
+    if num_outports != 1:
+      errors.append(f"Delay block must have one inport, instead got {num_outports}")
+      out_type = None
+    else:
+      out_type = get_type_name(get_target(get_outgoing(this, "hasOutPort")[0]))
+    if in_type != None and out_type != None and in_type[0:3] != out_type[0:3]:
+      errors.append(f"Inport type ({in_type}) differs from outport type ({out_type})")
+    errors
+  ```;
+}
+:Inheritance (Delay -> Block)
+
+
+
+
+# Object Diagrams are statically typed, so we must create in/out-ports, and MemorySlots for all primitive types:
+
+
+# Port types
+
+BoolInPort:Class
+IntInPort:Class
+StrInPort:Class
+
+BoolOutPort:Class
+IntOutPort:Class
+StrOutPort:Class
+
+:Inheritance (BoolInPort -> InPort)
+:Inheritance (IntInPort -> InPort)
+:Inheritance (StrInPort -> InPort)
+
+:Inheritance (BoolOutPort -> OutPort)
+:Inheritance (IntOutPort -> OutPort)
+:Inheritance (StrOutPort -> OutPort)
+
+# Link types
+
+boolLink:Association (BoolOutPort -> BoolInPort)
+intLink:Association (IntOutPort -> IntInPort)
+strLink:Association (StrOutPort -> StrInPort)
+
+:Inheritance (boolLink -> link)
+:Inheritance (intLink -> link)
+:Inheritance (strLink -> link)
+
+# Delay block types
+
+BoolDelay:Class
+IntDelay:Class
+StrDelay:Class
+
+:Inheritance (BoolDelay -> Delay)
+:Inheritance (IntDelay -> Delay)
+:Inheritance (StrDelay -> Delay)

examples/cbd/models/mm_runtime.od

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+# Link state ("signal")
+# is optional: absent for yet-to-compute signals
+
+intLink_signal:AttributeLink (intLink -> Integer) {
+  name = "signal";
+  optional = True;
+}
+boolLink_signal:AttributeLink (boolLink -> Boolean) {
+  name = "signal";
+  optional = True;
+}
+strLink_signal:AttributeLink (strLink -> String) {
+  name = "signal";
+  optional = True;
+}
+
+
+
+# Delay block state
+# mandatory - otherwise we cannot determine the output signal of a delay block
+
+State:Class {
+  abstract = True;
+}
+
+delay2State:Association (Delay -> State) {
+  source_lower_cardinality = 1;
+  source_upper_cardinality = 1;
+  target_lower_cardinality = 1;
+  target_upper_cardinality = 1;
+}
+
+BoolState:Class
+IntState:Class
+StrState:Class
+
+:Inheritance (BoolState -> State)
+:Inheritance (IntState -> State)
+:Inheritance (StrState -> State)
+
+
+BoolState_state:AttributeLink (BoolState -> Boolean) {
+  name = "state";
+  optional = False;
+}
+
+IntState_state:AttributeLink (IntState -> Integer) {
+  name = "state";
+  optional = False;
+}
+
+StrState_state:AttributeLink (StrState -> String) {
+  name = "state";
+  optional = False;
+}