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Yentl Van Tendeloo
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src/pypdevs/minimal.py
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237
src/pypdevs/minimal.py
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# Copyright 2015 Modelling, Simulation and Design Lab (MSDL) at
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# McGill University and the University of Antwerp (http://msdl.cs.mcgill.ca/)
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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"""
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The minimal PythonPDEVS simulation kernel. It only supports simple Parallel DEVS simulation, without any fancy configuration options.
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While it behaves exactly the same as the normal simulation kernel with default options, it is a lot faster due to skipping all features.
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"""
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from collections import defaultdict
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from pypdevs.DEVS import CoupledDEVS, AtomicDEVS, RootDEVS
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"""
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# Uncomment this part to make a completely stand-alone simulation kernel
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class BaseDEVS(object):
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def __init__(self, name):
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self.name = name
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self.IPorts = []
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self.OPorts = []
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self.ports = []
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self.parent = None
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self.time_last = (0.0, 0)
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self.time_next = (0.0, 1)
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self.my_input = {}
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def addPort(self, name, is_input):
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name = name if name is not None else "port%s" % len(self.ports)
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port = Port(is_input=is_input, name=name)
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if is_input:
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self.IPorts.append(port)
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else:
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self.OPorts.append(port)
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port.port_id = len(self.ports)
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self.ports.append(port)
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port.host_DEVS = self
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return port
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def addInPort(self, name=None):
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return self.addPort(name, True)
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def addOutPort(self, name=None):
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return self.addPort(name, False)
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def getModelName(self):
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return self.name
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def getModelFullName(self):
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return self.full_name
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class AtomicDEVS(BaseDEVS):
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ID = 0
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def __init__(self, name):
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BaseDEVS.__init__(self, name)
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self.elapsed = 0.0
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self.state = None
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self.model_id = AtomicDEVS.ID
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AtomicDEVS.ID += 1
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def extTransition(self, inputs):
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return self.state
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def intTransition(self):
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return self.state
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def confTransition(self, inputs):
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self.state = self.intTransition()
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return self.extTransition(inputs)
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def timeAdvance(self):
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return float('inf')
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def outputFnc(self):
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return {}
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class CoupledDEVS(BaseDEVS):
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def __init__(self, name):
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BaseDEVS.__init__(self, name)
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self.component_set = []
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def addSubModel(self, model):
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model.parent = self
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self.component_set.append(model)
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return model
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def connectPorts(self, p1, p2):
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p1.outline.append(p2)
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p2.inline.append(p1)
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class RootDEVS(object):
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def __init__(self, components, scheduler):
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self.component_set = components
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self.time_next = float('inf')
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self.scheduler = scheduler(self.component_set, 1e-6, len(self.component_set))
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class Port(object):
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def __init__(self, is_input, name=None):
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self.inline = []
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self.outline = []
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self.host_DEVS = None
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self.name = name
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def getPortname(self):
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return self.name
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"""
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def directConnect(component_set):
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"""
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Perform a trimmed down version of the direct connection algorithm.
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It does not support transfer functions, but all the rest is the same.
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:param component_set: the iterable to direct connect
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:returns: the direct connected component_set
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"""
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new_list = []
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for i in component_set:
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if isinstance(i, CoupledDEVS):
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component_set.extend(i.component_set)
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else:
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# Found an atomic model
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new_list.append(i)
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component_set = new_list
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# All and only all atomic models are now direct children of this model
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for i in component_set:
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# Remap the output ports
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for outport in i.OPorts:
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# The new contents of the line
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outport.routing_outline = set()
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worklist = list(outport.outline)
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for outline in worklist:
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# If it is a coupled model, we must expand this model
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if isinstance(outline.host_DEVS, CoupledDEVS):
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worklist.extend(outline.outline)
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else:
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outport.routing_outline.add(outline)
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outport.routing_outline = list(outport.routing_outline)
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return component_set
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class Simulator(object):
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"""
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Minimal simulation kernel, offering only setTerminationTime and simulate.
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Use this Simulator instead of the normal one to use the minimal kernel.
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While it has a lot less features, its performance is much higher.
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The polymorphic scheduler is also used by default.
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"""
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def __init__(self, model):
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"""
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Constructor
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:param model: the model to simulate
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"""
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if isinstance(model, CoupledDEVS):
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component_set = directConnect(model.component_set)
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ids = 0
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for m in component_set:
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m.time_last = (-m.elapsed, 0)
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m.time_next = (-m.elapsed + m.timeAdvance(), 1)
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m.model_id = ids
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ids += 1
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self.model = RootDEVS(component_set, component_set, None)
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elif isinstance(model, AtomicDEVS):
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for p in model.OPorts:
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p.routing_outline = []
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model.time_last = (-model.elapsed, 0)
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model.time_next = (model.time_last[0] + model.timeAdvance(), 1)
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model.model_id = 0
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self.model = RootDEVS([model], [model], None)
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self.termination_time = float('inf')
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def setTerminationTime(self, time):
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"""
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Set the termination time of the simulation.
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:param time: simulation time at which simulation should terminate
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"""
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self.termination_time = time
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def simulate(self):
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"""
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Perform the simulation
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"""
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from schedulers.schedulerAuto import SchedulerAuto
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scheduler = SchedulerAuto(self.model.component_set, 1e-6, len(self.model.component_set))
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tn = scheduler.readFirst()
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tt = self.termination_time
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while tt > tn[0]:
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# Generate outputs
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transitioning = defaultdict(int)
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for c in scheduler.getImminent(tn):
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transitioning[c] |= 1
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outbag = c.outputFnc()
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for outport in outbag:
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p = outbag[outport]
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for inport in outport.routing_outline:
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inport.host_DEVS.my_input.setdefault(inport, []).extend(p)
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transitioning[inport.host_DEVS] |= 2
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# Perform transitions
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for aDEVS, ttype in transitioning.iteritems():
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if ttype == 1:
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aDEVS.state = aDEVS.intTransition()
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elif ttype == 2:
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aDEVS.elapsed = tn[0] - aDEVS.time_last[0]
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aDEVS.state = aDEVS.extTransition(aDEVS.my_input)
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elif ttype == 3:
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aDEVS.elapsed = 0.
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aDEVS.state = aDEVS.confTransition(aDEVS.my_input)
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aDEVS.time_next = (tn[0] + aDEVS.timeAdvance(), 1 if tn[0] > aDEVS.time_last[0] else tn[1] + 1)
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aDEVS.time_last = tn
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aDEVS.my_input = {}
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# Do reschedules
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scheduler.massReschedule(transitioning)
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tn = scheduler.readFirst()
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def __getattr__(self, attr):
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"""
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Wrapper to inform users that they are using the minimal kernel if they zant to do some unsupported configuration option.
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"""
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if attr.startswith("set"):
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raise Exception("You are using the minimal simulation kernel, which does not support any configuration except for the termination time. Please switch to the normal simulation kernel to use this option.")
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else:
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raise AttributeError()
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